SH7205 Datasheet, PDF (1196/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.11 FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR)
These registers determine whether or not writing to the buffer memory has been finished, the
buffer on the CPU side has been cleared, and the FIFO port is accessible. CFIFOCTR,
D0FIFOCTR, and D1FIFOCTR are provided for the corresponding FIFO ports.
These registers are initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BVAL BCLR FRDY —
DTLN[11:0]
Initial value: 0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W*¹ R/W*² R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name
Value R/W Description
15
BVAL
0
R/W*¹ Buffer Memory Valid Flag
When the pipe selected by the CURPIPE bits is in
the transmitting direction, set this bit to 1 in the
following cases. Then, this module switches the
FIFO buffer from the CPU side to the SIE side,
enabling transmission.
• When transmitting a short packet, set this bit to 1
after data has been written.
• When transmitting a zero-length packet, set this
bit to 1 before data is written to the FIFO buffer.
• Set this bit to 1 after the number of data bytes
has been written for the pipe in continuous
transfer mode, where the number is a natural
integer multiple of the maximum packet size and
less than the buffer size.
When the data of the maximum packet size has been
written for the pipe in non-continuous transfer mode,
this module sets this bit to 1 and switches the FIFO
buffer from the CPU side to the SIE side, enabling
transmission.
0: Invalid
1: Writing ended
Note: Writing 1 to this bit should be done while FRDY
indicates 1 (set by this module). When the
specified pipe is in the receiving direction, do
not set this bit to 1.
Rev. 1.00 Mar. 25, 2008 Page 1164 of 1868
REJ09B0372-0100