SH7205 Datasheet, PDF (831/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 Synchronous Serial Communication Unit (SSU)
Section 17 Synchronous Serial Communication Unit (SSU)
This LSI has two synchronous serial communication unit (SSU) channels. The SSU has master
mode in which this LSI outputs clocks as a master device for synchronous serial communication
and slave mode in which clocks are input from an external device for synchronous serial
communication. Synchronous serial communication can be performed with devices having
different clock polarity and clock phase.
17.1 Features
• Choice of SSU mode and clock synchronous mode
• Choice of master mode and slave mode
• Choice of standard mode and bidirectional mode
• Synchronous serial communication with devices with different clock polarity and clock phase
• Choice of 8/16/32-bit width of transmit/receive data
• Full-duplex communication capability
The shift register is incorporated, enabling transmission and reception to be executed
simultaneously.
• Consecutive serial communication
• Choice of LSB-first or MSB-first transfer
• Choice of a clock source
Pφ/4, Pφ/8, Pφ/16, Pφ/32, Pφ/64, Pφ/128, Pφ/256, or an external clock
• Five interrupt sources
Transmit end, transmit data register empty, receive data full, overrun error, and conflict error.
The direct memory access controller (DMAC) can be activated by a transmit data register
empty request or a receive data full request to transfer data.
• Module standby mode can be set
To reduce power consumption, the operation of the SSU can be suspended by stopping the
clock supply to the SSU.
Rev. 1.00 Mar. 25, 2008 Page 799 of 1868
REJ09B0372-0100