SH7205 Datasheet, PDF (25/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

23.3.4 Address Register (FLADR) ................................................................................ 1081
23.3.5 Address Register 2 (FLADR2) ........................................................................... 1083
23.3.6 Data Counter Register (FLDTCNTR)................................................................. 1084
23.3.7 Data Register (FLDATAR)................................................................................. 1085
23.3.8 Interrupt DMA Control Register (FLINTDMACR) ........................................... 1086
23.3.9 Ready Busy Timeout Setting Register (FLBSYTMR) ....................................... 1092
23.3.10 Ready Busy Timeout Counter (FLBSYCNT)..................................................... 1093
23.3.11 Data FIFO Register (FLDTFIFO)....................................................................... 1094
23.3.12 Control Code FIFO Register (FLECFIFO) ......................................................... 1095
23.3.13 Transfer Control Register (FLTRCR)................................................................. 1096
23.3.14 4-Symbol ECC Processing Result Register n (FL4ECCRESn) (n = 1 to 4) ....... 1097
23.3.15 4-Symbol ECC Control Register (FL4ECCCR) ................................................. 1099
23.3.16 4-Symbol ECC Error Count Register (FL4ECCCNT)........................................ 1100
23.4 Operation ......................................................................................................................... 1102
23.4.1 Access Sequence................................................................................................. 1102
23.4.2 Operating Modes................................................................................................. 1103
23.4.3 Register Setting Procedure.................................................................................. 1104
23.4.4 Command Access Mode ..................................................................................... 1105
23.4.5 Sector Access Mode............................................................................................ 1110
23.4.6 ECC Error Correction ......................................................................................... 1112
23.4.7 Status Read ......................................................................................................... 1117
23.5 Interrupt Sources.............................................................................................................. 1119
23.6 DMA Transfer Specifications .......................................................................................... 1120
23.7 Usage Notes ..................................................................................................................... 1121
23.7.1 Writing to the Control-Code Area when 4-Symbol ECC Circuit is in Use......... 1121
Section 24 USB 2.0 Host/Function Module (USB) .........................................1123
24.1 Features............................................................................................................................ 1123
24.2 Input/Output Pins ............................................................................................................. 1126
24.3 Register Description......................................................................................................... 1128
24.3.1 System Configuration Control Register 0 (SYSCFG0) ...................................... 1132
24.3.2 System Configuration Control Register 1 (SYSCFG1) ...................................... 1136
24.3.3 System Configuration Status Register 0 (SYSSTS0).......................................... 1138
24.3.4 System Configuration Status Register 1 (SYSSTS1).......................................... 1139
24.3.5 Device State Control Register 0 (DVSTCTR0) .................................................. 1141
24.3.6 Device State Control Register 1 (DVSTCTR1) .................................................. 1146
24.3.7 Test Mode Register (TESTMODE) .................................................................... 1150
24.3.8 DMA-FIFO Bus Configuration Registers (D0FBCFG, D1FBCFG) .................. 1153
24.3.9 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO) .............................................. 1154
24.3.10 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)............... 1156
Rev. 1.00 Mar. 25, 2008 Page xxv of xxxii