SH7205 Datasheet, PDF (1202/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value
R/W Description
10 to 7 
Undefined R
Reserved
Undefined values are read from these bits. The write
value should always be 0.
6
EOFERRE 0
R/W PORT0 EOF Error Detection Interrupt Enable
Enables/disables the interrupt request when PORT0
EOFERR interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
5
SIGNE
0
R/W PORT0 Setup Transaction Error Interrupt Enable
Enables/disables the interrupt request when SIGN
interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
4
SACKE
0
R/W PORT0 Setup Transaction Normal Response
Interrupt Enable
Enables/disables the interrupt request when SACK
interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
3 to 0 
Undefined R
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Note: Clear each bit in this register to 0 when the function controller function is selected.
Rev. 1.00 Mar. 25, 2008 Page 1170 of 1868
REJ09B0372-0100