SH7205 Datasheet, PDF (1256/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value
R/W Description
8
CNTMD
0
R/W Continuous Transfer Mode*
Specifies whether to use the selected pipe in
continuous transfer mode. This bit is valid when any
one of PIPE1 to PIPE5 is selected and also bulk
transfer is selected.
This module determines the completion of
transmission or reception for the FIFO buffer
assigned to the selected pipe as shown in table
24.12 according to the setting of this bit.
0: Non-continuous transfer mode
1: Continuous transfer mode
7
SHTNAK 0
R/W Pipe Disable at End of Transfer*
Specifies whether to modify PID to NAK upon the
end of transfer when the selected pipe is in the
receiving direction. This bit is valid when the selected
pipe is one of PIPE1 to PIPE5 and is in the receiving
direction.
When this bit is set to 1 for the pipe in the receiving
direction, this module modifies the PID bits
corresponding to the selected pipe to NAK on
determining the end of the transfer. This module
determines that the transfer has ended in either of
the following conditions.
• A short packet (including a zero-length packet) is
successfully received.
• The transaction counter is used and the number
of packets specified by the counter is
successfully received.
0: Pipe continued at the end of transfer
1: Pipe disabled at the end of transfer
Note: This bit should be cleared to 0 for the pipe in
the transmitting direction.
6, 5

Undefined R
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1224 of 1868
REJ09B0372-0100