SH7205 Datasheet, PDF (534/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.9 Timer A/D Converter Start Request Control Register (TADCR)
TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests
and specifies whether to link A/D converter start requests with interrupt skipping operation. The
MTU2 has one TADCR in channel 4.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BF[1:0]
-
-
-
-
-
- UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE
Initial value: 0
0
0
0
0
0
0
0
0 0* 0 0* 0* 0* 0* 0*
R/W: R/W R/W R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Note: * Do not set to 1 when complementary PWM mode is not selected.
Bit
Bit Name
15, 14 BF[1:0]
13 to 8 —
7
UT4AE
6
DT4AE
Initial
Value
00
All 0
0
0*
R/W
R/W
R
R/W
R/W
Description
TADCOBRA_4/TADCOBRB_4 Transfer Timing Select
Select the timing for transferring data from
TADCOBRA_4 and TADCOBRB_4 to TADCORA_4
and TADCORB_4.
For details, see table 12.27.
Reserved
These bits are always read as 0. The write value should
always be 0.
Up-Count TRG4AN Enable
Enables or disables A/D converter start requests
(TRG4AN) during TCNT_4 up-count operation.
0: A/D converter start requests (TRG4AN) disabled
during TCNT_4 up-count operation
1: A/D converter start requests (TRG4AN) enabled
during TCNT_4 up-count operation
Down-Count TRG4AN Enable
Enables or disables A/D converter start requests
(TRG4AN) during TCNT_4 down-count operation.
0: A/D converter start requests (TRG4AN) disabled
during TCNT_4 down-count operation
1: A/D converter start requests (TRG4AN) enabled
during TCNT_4 down-count operation
Rev. 1.00 Mar. 25, 2008 Page 502 of 1868
REJ09B0372-0100