SH7205 Datasheet, PDF (972/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
• Mailbox-0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0 NMC 0
0
MBC[2:0]
0
0
0
0
DLC[3:0]
Initial value: 0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
R/W: R
R R/W R
R R/W R R/W R
R
R
R R/W R/W R/W R/W
Note: MBC[1] of MB0 is always "1".
• Mailbox-31 to 1
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0 NMC ATX DART
MBC[2:0]
0
0
0
0
DLC[3:0]
Initial value: 0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
R/W: R
R R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W R/W R/W
NMC (New Message Control): When this bit is set to ‘0’, the Mailbox of which the RXPR or
RFPR bit is already set does not store the new message but maintains the old one and sets the
UMSR correspondent bit. When this bit is set to ‘1’, the Mailbox of which the RXPR or RFPR bit
is already set overwrites with the new message and sets the UMSR correspondent bit.
Important: Please note that if a remote frame is overwritten with a data frame or vice versa could
be that both RXPR and RFPR flags (together with UMSR) are set for the same Mailbox. In this
case the RTR bit within the Mailbox Control Field should be relied upon.
Important: Please note that when the Time Triggered mode is used NMC needs to be set to ‘1’
for Mailbox 31 to allow synchronization with all incoming reference messages even when
RXPR[31] is not cleared.
NMC
0
1
Description
Overrun mode (Initial value)
Overwrite mode
Rev. 1.00 Mar. 25, 2008 Page 940 of 1868
REJ09B0372-0100