SH7205 Datasheet, PDF (349/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
(3) SDRAMC Register Setting Conditions
Rewriting of SDRAMC registers should only be performed when all of the conditions listed in
table 10.10 are satisfied.
Table 10.10 Register Rewrite Conditions
Function/Operation Register Name Conditions
Self-refresh
SDRFCNT0
• SDRAM access disabled (set in SDRAMCm*¹)
• Auto-refresh enabled (DRFEN = 1)
• Power-down disabled (DPWD/DPWDCI = 0)
• Deep-power-down disabled (DDPD/DDPDCI = 0)
Auto-refresh
SDRFCNT1 • Self-refresh disabled (DSFEN/DSFENCI = 0)
• Power-down disabled (DPWD/DPWDCI = 0)
Initialization sequence SDIR0
• Before start of initialization sequence
SDIR1
• After reset or after recovery from deep-power-down
Power-down
SDPWDCNT • SDRAM access disabled (set in SDRAMCm*¹)
• Auto-refresh enabled (DRFEN = 1)
• Self-refresh disabled (DSFEN/DSFENCI = 0)
• Deep-power-down disabled (DDPD/DDPDCI = 0)
Deep-power-down
SDDPDCNT • SDRAM access disabled (set in SDRAMCm*¹)
• Self-refresh disabled (DSFEN/DSFENCI = 0)
• Auto-refresh disabled (DRFEN = 0)
• Power-down disabled (DPWD/DPWDCI = 0)
Address register settings SD0ADR,
SD1ADR
• Auto-refresh disabled (DRFEN = 0)
• SDRAM access disabled (set in SDRAMCm*¹)
• Self-refresh disabled (DSFEN/DSFENCI = 0)
• Power-down disabled (DPWD/DPWDCI = 0)
• Deep-power-down disabled (DDPD/DDPDCI = 0)
Timing register settings SD0TR, SD1TR • Self-refresh in progress (DSFEN/DSFENCI = 1)
or
• Self-refresh disabled (DSFEN/DSFENCI = 0)
• Auto-refresh disabled (DRFEN = 0)
• SDRAM access disabled (set in SDRAMCm*¹)
Rev. 1.00 Mar. 25, 2008 Page 317 of 1868
REJ09B0372-0100