SH7205 Datasheet, PDF (209/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.3.7 PINT Interrupt Request Registers (C0PIRR, C1PIRR)
C0PIRR and C1PIRR are 16-bit registers that indicate interrupt requests from external interrupt
input pins PINT7 to PINT0.
However, this register is enabled only when C0PINTER and C1PINTER accept an interrupt
request input. When an interrupt request input is disabled, this register always becomes 0.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
- PINT7R PINT6R PINT5R PINT4R PINT3R PINT2R PINT1R PINT0R
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
Bit
15 to 8
Bit Name

Initial
Value
All 0
7
PINT7R 0
6
PINT6R 0
5
PINT5R 0
4
PINT4R 0
3
PINT3R 0
2
PINT2R 0
1
PINT1R 0
0
PINT0R 0
[Legend]
n = 7 to 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R
PINT Interrupt Request
R
These bits indicate the status of the PINT7 to PINT0
R
interrupt requests.
R
0: No interrupt request at PINTn pin
R
1: Interrupt request at PINTn pin
R
R
R
Rev. 1.00 Mar. 25, 2008 Page 177 of 1868
REJ09B0372-0100