SH7205 Datasheet, PDF (1224/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
(a) Short Packet, Including Zero-Length Packet, has been Received
(b) Packets for the Value Set in Bits TRNCNT have been Received When the Transaction
Counter (Bits TRNCNT) is Used
When either of the above conditions is satisfied and reading of that data has been completed, this
module determines that all the data for one round of transfer have been read out.
If a zero-length packet is received while the FIFO buffer is empty, this module this module
determines that all the data for one round of transfer have been read out at the point when the zero-
length packet data has been toggled to the CPU side. In this case, the next transfer can be started
by writing 1 to the BCLR bit in the corresponding FIFOCTR register.
With this setting, the BRDY interrupt is not detected for transmitting pipes.
The BRDY interrupt status bit of the pertinent pipe can be cleared by writing 0 to the bit
corresponding to the pipe in this register.
When this mode is used, do not modify the BFRE bit setting until the processing for that round of
transfer is completed. To modify the BFRE bit, use the ACLRM bit to clear all the contents of the
FIFO buffer of the corresponding pipe.
(3) When BRDYM = 1 and BFRE = 0 are Set
With this setting, the values of the bits in this register reflect the value of the BSTS bit of the
individual pipes. This means that the BRDY interrupt statuses are set according to the states of the
FIFO buffers.
(a) Condition for Pipes in the Transmitting Direction
When data writing to the FIFO port is possible, the corresponding bit in this register is set to 1.
When not possible, the bit is cleared to 0. For the transmitting DCP, however, the BRDY interrupt
is not generated even if writing is possible.
(b) Condition for Pipes in the Receiving Direction
When data reading from the FIFO port is possible, the corresponding bit in this register is set to 1.
After all the data have been read out (when reading has become not possible), the bit is cleared to
0. If a zero-length packet is received while the FIFO buffer is empty, the corresponding bit is set
to 1 until 1 is written to BCLR, during which the BRDY interrupt is continuously generated.
With this setting, the status bits in this register cannot be cleared by writing 0.
When BRDYM = 1 is set, all the BFRE bits (for all pipes) must be cleared to 0.
Rev. 1.00 Mar. 25, 2008 Page 1192 of 1868
REJ09B0372-0100