SH7205 Datasheet, PDF (1108/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
Bit
9
8 to 4
3
2, 1
0
Initial
Bit Name Value R/W
NANDWF 0
R/W
—
All 0
R
CE
0
R/W
—
All 0
R
TYPESEL 0
R/W
Description
NAND Wait Insertion Operation
0: Performs address or data input/output in one FCLK
cycle
1: Performs address or data input/output in two FCLK
cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
Chip Enable
0: Disables the chip (Outputs high level to the FCE pin)
1: Enables the chip (Outputs low level to the FCE pin)
Reserved
These bits are always read as 0. The write value should
always be 0.
Memory Select
0: AND-type flash memory is selected
1: NAND-type flash memory or AG-AND is selected
Rev. 1.00 Mar. 25, 2008 Page 1076 of 1868
REJ09B0372-0100