SH7205 Datasheet, PDF (1336/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
25.3.2 ATAPI Interface Control Register Map
[Legend]
Initial value: Register value after power-on reset
:
Undefined value
R/W:
Readable and writable bit. The write value can be read.
R/WC0:
Readable and writable bit. If 0 is written, the bit is initialized. If 1 is written, it is
ignored.
R:
Read-only register; only 0 should be written unless otherwise stated.
/W:
Write-only bit. The read value is undefined.
All control/status registers are active high.
(1) ATAPI control register (ATAPI_CONTROL)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
- DTCD - RESET M/S
- UDMAEN -
R/W STOP START
Initial value: -
-
-
-
-
-
0
-
0
0
1
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R R/W R/W R R/W R R/W R/W R/W
Bit
Bit Name
31 to 10 
Initial
Value

R/W Description
R
Reserved
Rev. 1.00 Mar. 25, 2008 Page 1304 of 1868
REJ09B0372-0100