SH7205 Datasheet, PDF (1170/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.3 System Configuration Status Register 0 (SYSSTS0)
SYSSTS0 is a register that monitors the line status (D+ and D− lines) of the USB data bus on
PORT0.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LNST[1:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
*
*
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value
R/W Description
15 to 2 
Undefined R
Reserved
Undefined values are read from these bits. The write
value should always be 0.
1, 0
LNST[1:0] *
R
PORT0 USB Data Line Status
The statuses of the USB data bus lines (D+ and D-)
of this module are listed in table 24.5.
The USB data bus line status of PORT0 can be
monitored by reading the value of these bits.
Note: These bits should be read after setting DPRPU
to 1 to notify connection when the function
controller function is selected; whereas after
setting DRPD to 1 to enable pulling down the
lines when the host controller function is
selected.
Note: * Depends on the states of the D+ and D- lines.
Rev. 1.00 Mar. 25, 2008 Page 1138 of 1868
REJ09B0372-0100