SH7205 Datasheet, PDF (1258/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Table 24.12 CNTMD Bit Setting and Method of Determining Completion of
Transmission/Reception for the FIFO Buffer
CNTMD Bit
Setting
0
1
Method of Determining Readiness for Reading and Transmission
Condition for the FIFO buffer being ready for reading when set for receiving
direction (DIR = 0):
• This controller receives one packet.
Conditions for the FIFO buffer being ready for transmission when set for
transmitting direction (DIR = 1):
When either of the following conditions is met
(1) The maximum packet size of data is written to the FIFO buffer.
(2) Data for a short packet (including 0 bytes) is written to the FIFO buffer and
1 is written to BVAL.
Conditions for the FIFO buffer being ready for reading when set for receiving
direction (DIR = 0):
(1) The number of received data bytes in the FIFO buffer assigned to the
selected pipe has become equal to the allocated number of bytes
([BUFSIZE + 1) × 64).
(2) This controller receives a short packet other than a zero-length packet.
(3) This controller receives a zero-length packet when data is already stored
in the FIFO buffer assigned to the selected pipe.
(4) This controller has received packets of the number of times set in the
transaction counter for the selected pipe.
Conditions for the FIFO buffer being ready for transmission when set for
transmitting direction (DIR = 1):
When any of the following conditions is met
(1) The number of data bytes written to the FIFO buffer has become equal to
the size of one plane of the FIFO buffer assigned to the selected pipe.
(2) Data of the size smaller than the size of one plane of the FIFO buffer
assigned to the selected pipe (including 0 bytes) is written to the FIFO
buffer and 1 is written to BVAL.
(3) With the DMA transfer end sampling enable bit (TENDE) set to 1, data of
the size smaller than the size of one plane of the FIFO buffer assigned to
the selected pipe (including 0 bytes) is written to the FIFO buffer by DMA
transfer and 1 is written to BVAL.
Rev. 1.00 Mar. 25, 2008 Page 1226 of 1868
REJ09B0372-0100