SH7205 Datasheet, PDF (414/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.6 _{DMA Reload Byte Count Register (DMRBCTn)}
DMRBCTn is a register used to set the byte count to be reloaded to the DMA current byte count
register (DMCBCTn). To enable the reload function, set the DMA byte count reload function
enable bit (BRLOD) in DMA control register A (DMCNTAn) to 1. In this case, set both the DMA
current byte count register (DMCBTn) and DMA reload byte count register (DMRBCTn).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
RBC[25:16]
Initial value: 0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RBC[15:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 26 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
25 to 0 RBC[25:0] Undefined R/W Number of DMA transfer bytes for reloading
Note:
Set this register so that the byte count becomes 0 as follows when the final data is sent in a
DMA transfer:
• When the transfer data size is set to 16 bits (SZSEL = 001): (bit 0) = 0
• When the transfer data size is set to 32 bits (SZSEL = 010): (bit 1, bit 0) = (0, 0)
Rev. 1.00 Mar. 25, 2008 Page 382 of 1868
REJ09B0372-0100