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SH7205 Datasheet, PDF (435/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Section 11 Direct Memory Access Controller (DMAC)
Note:
If the software trigger is selected as the DMA request source, the DMA request bit (DREQ)
can be set to 1 regardless of the settings of the DMA transfer enable bit (DEN) and DMAC
module activate bit (DMST) and the operand transfer status. However, even if the software
trigger is selected as the DMA request source, clear the DMA request bit (DREQ) to 0 or
write data to the DMAC internal state clear bit (DSCLR) only when the corresponding
channel is not engaged in single operand transfer (the corresponding DASTS bit in the
DMA arbitration status register (DMASTS) is 0) and DMA transfer is disabled (the DMST bit
in the DMA activation control register (DMSCNT) is 0 or the DEN bit in DMA control register
B (DMCNTBn) is 0). In other cases, operation is not guaranteed when data is written to this
register.
11.3.10 DMA Activation Control Register (DMSCNT)
DMSCNT controls the entire DMAC operation.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- DMST
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value
31 to 17 
All 0
16
DMST 0
15 to 0 
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should always
be 0.
R/W DMAC Module Activate
This bit is used to set DMAC module operation/stop. Clearing
this bit to 0 stops the DMAC. Setting this bit to 1 activates the
DMAC (for details, see section 11.4.3, DMA Activation, and
section 11.6, Suspending, Restarting, and Stopping of DMA
Transfer).
0: DMAC stops
1: DMAC operates
R Reserved
These bits are always read as 0. The write value should always
be 0.
Rev. 1.00 Mar. 25, 2008 Page 403 of 1868
REJ09B0372-0100