SH7205 Datasheet, PDF (1598/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
30.2.25 Deep Standby Cancel Source Select Register (DSSSR)
DSSSR is a 16-bit readable/writable register that consists of the bits for selecting the interrupt to
cancel deep standby mode. IRQ7 to IRQ0 bits are valid only for pins allocated to PJ3 to PJ0 and
PC3 to PC0.
Note: When writing to this register, see section 30.4, Usage Notes.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
- MRES IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 9 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
MRES 0
R/W Return from Deep Standby Mode by Manual Reset
0: The system does not return from deep standby mode by a
manual reset.
1: The system returns from deep standby mode by a manual
reset.
7
IRQ7
0
R/W Return from Deep Standby Mode by IRQ7 (PJ3 only)
0: The system does not return from deep standby mode by
an IRQ7 interrupt.
1: The system returns from deep standby mode by an IRQ7
interrupt.
6
IRQ6
0
R/W Return from Deep Standby Mode by IRQ6 (PJ2 only)
0: The system does not return from deep standby mode by
an IRQ6 interrupt.
1: The system returns from deep standby mode by an IRQ6
interrupt.
5
IRQ5
0
R/W Return from Deep Standby Mode by IRQ5 (PJ1 only)
0: The system does not return from deep standby mode by
an IRQ5 interrupt.
1: The system returns from deep standby mode by an IRQ5
interrupt.
Rev. 1.00 Mar. 25, 2008 Page 1566 of 1868
REJ09B0372-0100