SH7205 Datasheet, PDF (1429/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
VICLK
VICLKENB
VIVSYNC
VIHSYNC
DCLKIN
27-MHz
image
processing
block
Data buffer
Write
control
Read
control
DCLKIN
panel
display
processing
block
RGB data
(After blending)
Field determination
The MVON bit in the
MGR_MIXMODE register
HS width setting register
Generation
of
VSYNC
_dck
Generation of
free-running
HSYNC_dck
EX
OR
CSYNC
DCLKIN
The period of HSYNC_dck is fixed. The period of VSYNC_dck varies within 1H at most.
Figure 26.11 SYNC Signal Generating Unit
(VICLK and DCLKIN Subsystems)
Rev. 1.00 Mar. 25, 2008 Page 1397 of 1868
REJ09B0372-0100