SH7205 Datasheet, PDF (1219/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Notes: 1. Only 1 can be written to.
2. The interrupts generated by the status transitions indicated by each bit in this register
should only be enabled when the host controller function is selected.
3. This module detects the change in the status indicated by the BCHG bit even while the
clock supply is stopped (while SCKE is 0), and outputs the corresponding interrupt
request as long as it is enabled. Clearing the status should be done after enabling the
clock supply.
24.3.21 Interrupt Status Register 2 (INTSTS2)
INTSTS2 indicates the statuses of various interrupts.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— BCHG — DTCH ATTCH —
—
—
—
EOF
ERR
—
—
—
—
—
—
Initial value: -
0
-
0
0
-
-
-
-
0
-
-
-
-
-
-
R/W: R R/W*¹ R R/W*¹ R/W*¹ R
R
R
R R/W*¹ R
RR
R
R
R
Initial
Bit
Bit Name Value
R/W Description
15

Undefined R
Reserved
Undefined value is read from this bit. The write value
should always be 0.
14
BCHG
0
R/W*¹ PORT1 USB Bus Change Interrupt Status*³
This bit is set to 1 when a transition in the full-speed
or low-speed signal level occurs on PORT1 (a
change from J-state, K-state, or SE0 to J-state, K-
state, or SE0). When a BCHG interrupt has occurred,
read the LNST bit several times and confirm that the
same value is read consecutively in order to prevent
chattering.
0: BCHG interrupt has not occurred
1: BCHG interrupt has occurred
13

Undefined R
Reserved
Undefined value is read from this bit. The write value
should always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1187 of 1868
REJ09B0372-0100