SH7205 Datasheet, PDF (1294/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
(3) USB Data Bus Resistor Control
This module controls switching of the pull-up resistor for the D+ signal and a pull-down resistor
for the D+ and D- signals. These signals can be pulled up or down using the DPRPU and DRPD
bits in SYSCFG0 (for PORT0) and DRPD bit in SYSCFG1 (for PORT1).
This module includes the terminal resistor for the D+ and D- signals during high-speed operation
and the output resistor for the signals during full-speed operation. This module automatically
switches the resistor after connection with the USB host or function device when reset handshake,
suspended state or resume is detected.
When the function controller function is selected and the DPRPU bit in SYSCFG0 is cleared to 0
during communication with the USB host, the pull-up resistor (or the terminal resistor) of the USB
data line is disabled. This allows notification of device disconnection to the USB host.
(4) Register Access Wait Control
The following restrictions apply to numbers of cycles for access to registers of this module below
SYSSTS0.
Waite control: The cycle time for consecutive access to registers of this module must be at least 80
ns.
To comply with this constraint, the BWIT[3:0] bits of the SYSCFG1 register must be set to apply
wait control for register access. Since the initial value is the largest value (17 clock cycles for a
cycle of access), select the optimal value.
Example of settings (1): Consecutive access to registers of this module
Bus-clock frequency: 66 MHz
Calculation: (2 cycles (access cycle for registers of this module) + 1 cycle (interval between
consecutive access operations) + BWAIT) × 1/66 MHz ≥ 80 ns
BWAIT = 3
Example of settings (2): Transfer of data from internal memory to the FIFO port registers
Bus-clock frequency: 66 MHz
Calculation: (2 cycles (access cycle for registers of this module) + 2 cycles (access cycle for
internal memory) + BWAIT) × 1/66 MHz ≥ 80 ns
BWAIT = 2
Rev. 1.00 Mar. 25, 2008 Page 1262 of 1868
REJ09B0372-0100