SH7205 Datasheet, PDF (719/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT)
14.3.2 Watchdog Timer Control/Status Register (WTCSR0, WTCSR1)
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
count, overflow flags, and timer enable bit.
Use word access to write to WTCSR with H'A5 set in the upper byte. Use byte access to read from
WTCSR.
Note: The method for writing to WTCSR differs from that for other registers to prevent
erroneous writes. See section 14.3.4, Notes on Register Access, for details.
Bit: 7
6
5
4
IOVF WT/IT TME
-
Initial value: 0
0
0
1
R/W: R/(W) R/W R/W R
3
2
1
0
-
CKS[2:0]
1
0
0
0
R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
IOVF
0
R/(W) Interval Timer Overflow
Indicates that WTCNT has overflowed in interval timer
mode. This flag is not set in watchdog timer mode.
0: No overflow
1: WTCNT overflow in interval timer mode
[Clearing condition]
• When 0 is written to IOVF after reading IOVF
6
WT/IT
0
R/W Timer Mode Select
Selects whether to use the WDT as a watchdog timer
or an interval timer.
0: Use as interval timer
1: Use as watchdog timer
Note: When the WTCNT overflows in watchdog timer
mode, the WDTOVF signal is output externally.
If this bit is modified when the WDT is running,
the up-count may not be performed correctly.
Rev. 1.00 Mar. 25, 2008 Page 687 of 1868
REJ09B0372-0100