SH7205 Datasheet, PDF (181/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
6.6 Interrupts
6.6.1 Interrupt Sources
The interrupt sources that trigger interrupt exception handling are NMI, user breaks, H-UDI, inter-
processor interrupts, IRQ, PINT, and on-chip peripheral modules.
Each interrupt source is assigned a different vector number and vector table offset. See table 7.8 in
section 7, Interrupt Controller (INTC), for more information on vector numbers and vector table
address offsets.
6.6.2 Interrupt Priority Level
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously
(overlap), the interrupt controller (INTC) determines their relative priorities and starts exception
handling according to the results.
The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest
and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is
always accepted. The user break interrupt and H-UDI interrupt priority level is 15. The inter-
processor interrupt has an interrupt priority level of 15 to 8 according to the interrupt source.
Priority levels of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be
set freely using the interrupt priority registers of the INTC (table 6.8). The priority levels that can
be set are 0 to 15. Level 16 cannot be set. See section 7.3.1, Interrupt Priority Registers 01, 02, 05
to 21 (C0IPR01, C0IPR02, C0IPR05 to C0IPR21, C1IPR01, C1IPR02, C1IPR05 to C1IPR21), for
details of the interrupt priority registers.
Table 6.8 Interrupt Priority Order
Type
NMI
User break
H-UDI
Inter-processor interrupt
IRQ
PINT
On-chip peripheral module
Priority Level
16
15
15
15 to 8
0 to 15
Comment
Fixed priority level. Cannot be masked.
Fixed priority level
Fixed priority level
Fixed priority level
Set by interrupt priority registers
Rev. 1.00 Mar. 25, 2008 Page 149 of 1868
REJ09B0372-0100