SH7205 Datasheet, PDF (352/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
(5) Auto-Refresh
An auto-refresh cycle starts when the auto-refresh operation enable bit (DRFEN) in SDRAM
refresh control register 1 (SDRFCNT1) is set to 1. After that, refresh requests are issued at fixed
intervals according to the refresh counter, activating auto-refresh cycles. However, the activation
of auto-refresh cycles may sometimes be delayed because refresh requests are not accepted during
read or write accesses.
A refresh request is issued immediately when the auto-refresh operation enable bit (DRFEN) in
SDRAM refresh control register 1 (SDRFCNT1) is set to 1 if auto-refresh is enabled.
The refresh counter is halted in self-refresh or deep-power-down mode. After recovery from self-
refresh or deep-power-down mode, an auto-refresh cycle is activated, after which the counter
value is reset and the counter begins operating again.
Make auto-refresh settings in SDRAM refresh control register 1 (SDRFCNT1). Note that refresh
cycles affect SDRAM for all channels. Figure 10.10 shows an auto-refresh cycle timing example.
Auto-refresh cycle
CKIO
SDRAM command
RFA DSL DSL
DREFW
DSL: Deselect command
RFA: Auto-refresh command
Figure 10.10 Auto-Refresh Cycle Timing Example (DREFW Bits = 0010)
Rev. 1.00 Mar. 25, 2008 Page 320 of 1868
REJ09B0372-0100