SH7205 Datasheet, PDF (461/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
10. DMA interrupt control register (DMICNT)
 When an interrupt is used
11. DMA common interrupt control register (DMICNTA)
 When an interrupt is used
12. DMA transfer enable bit (DEN) of DMA control register B (DMCNTBn)
13. DMA activation control register (DMSCNT)
(2) DMA Activation
To enable DMA transfer on a channel, set the DMA transfer enable bit (DEN) of DMA control
register B (DMCNTBn) and the DMAC module activate bit (DMST) of the DMA activation
control register (DMSCNT) corresponding to the channel to 1.
If multiple DMA transfer requests are present, channel priorities are judged, the DMA request
corresponding to the highest-priority channel is accepted, and DMA transfer on the channel is
started.
Whether DMA requests are present can be checked from the DMA request bit (DREQ) of DMA
control register B (DMCNTBn).
When a DMA request is accepted and DMA transfer is started, the DMA arbitration status bit
(DASTS) of the channel corresponding to the DMA arbitration status register (DMASTS) is set to
1.
Rev. 1.00 Mar. 25, 2008 Page 429 of 1868
REJ09B0372-0100