SH7205 Datasheet, PDF (1069/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 21 A/D Converter (ADC)
21.3.1 A/D Data Registers A to H (ADDRA to ADDRH)
The sixteen A/D data registers, ADDRA to ADDRH, are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the ADDR
corresponding to the selected channel. The 10 bits of the result are stored in the upper bits (bits 15
to 6) of ADDR. Bits 5 to 0 of ADDR are reserved bits that are always read as 0.
Access to ADDR in 8-bit units is prohibited. ADDR must always be accessed in 16-bit units.
Table 21.3 indicates the pairings of analog input channels and ADDR.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value R/W
15 to 6
All 0
R
5 to 0 
All 0
R
Description
Bit data (10 bits)
Reserved
These bits are always read as 0. The write value
should always be 0.
Table 21.3 Analog Input Channels and ADDR
Analog Input Channel
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
A/D Data Register where Conversion Result is Stored
ADDRA
ADDRB
ADDRC
ADDRD
ADDRE
ADDRF
ADDRG
ADDRH
Rev. 1.00 Mar. 25, 2008 Page 1037 of 1868
REJ09B0372-0100