SH7205 Datasheet, PDF (1491/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
• αRGB444 (AF83 (H)) converted into a standard format
α: A (H) → A (H) R: F (H) → 3C (H) G: 8 (H) → 20 (H) B: 3 (H) → 0C (H)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
α value
R value
G value
B value
1010111110000011
α value (4 bits)
↓ (Unchanged)
α value (4 bits)
R value (4 bits)
↓ (×4)
R value (6 bits)
G value (4 bits)
↓ (×4)
G value (6 bits)
B value (4 bits)
↓ (×4)
B value (6 bits)
Bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
α value
R value
G value
B value
10101 11100 1 000000 01100
Figure 26.52 Pixel Format Conversion in Output Block (1)
• αRGB555 (F599 (H)) converted into a standard format
α: 1 (H) → CHG_A bit in register MGR_MIXMODE
R: 1D (H) → 3A (H) G: 0C (H) → 18 (H) B: 19 (H) → 32 (H)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
α
value
R value
G value
B value
111101011001100 1
α value (4 bits)
CHG_A bit
R value (5 bits)
↓ (×2)
R value (6 bits)
G value (5 bits)
↓ (×2)
G value (6 bits)
B value (5 bits)
↓ (×2)
B value (6 bits)
Bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
α value
R value
G value
B value
x x x x1 11010 0 110001 1001 0
Figure 26.53 Pixel Format Conversion in Output Block (2)
Rev. 1.00 Mar. 25, 2008 Page 1459 of 1868
REJ09B0372-0100