SH7205 Datasheet, PDF (1136/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.4.3 Register Setting Procedure
Figure 23.3 shows the register setting flow required for accessing the flash memory.
Start
Start the setting procedure after the
current transfer has been completed
No
FLTRCR = All 0?
Yes
Set FLCMNCR
When the fifth address data is output
in command access, FLADR2 should
also be set
Not required in sector access
Not required in reading.
Not required when FLDTFIFO is used.
Not required in reading
Not required in reading
Start the transfer
Set FLCMDCR
Set FLCMCDR
Set FLADR
Set FLDTCNTR
Set FLDATAR
Set FLINTDMACR
Set FLBSYTMR
Set FLDTFIFO
Set FLECFIFO
Except FLTRCR,
No
register settings completed?
Yes
Set FLTRCR to H'01
Wait until the transfer is completed
No
TREND in FLTRCR = 1?
Yes
Set FLTRCR to H'00
End
Figure 23.3 Register Setting Flow
Rev. 1.00 Mar. 25, 2008 Page 1104 of 1868
REJ09B0372-0100