SH7205 Datasheet, PDF (312/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.4.5 CSn Wait Control Register 1 (CS1WCNTn) (n = 0 to 5)
CS1WCNTn specifies the number of wait states to be inserted into the read/write cycle or page
read/page write cycle.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
CSRWAIT[4:0]
-
-
-
CSWWAIT[4:0]
Initial value: 0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
R/W: R
R
R R/W R/W R/W R/W R/W R
R
R R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
CSPRWAIT[2:0]
-
-
-
-
-
CSPWWAIT[2:0]
Initial value: 0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
R/W: R
R
R
R
R R/W R/W R/W R
R
R
R
R R/W R/W R/W
Bit
Bit Name
31 to 29 
28 to 24 CSRWAIT
[4:0]
23 to 21 
20 to 16 CSWWAIT
[4:0]
15 to 11 
Initial
Value R/W
All 0 R
11111 R/W
All 0 R
11111 R/W
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Read Cycle Wait Select
These bits specify the number of wait states to be inserted
into the initial normal read cycle and page read cycle.
00000: 0 wait states
:
11111: 31 wait states
Reserved
These bits are always read as 0. The write value should
always be 0.
Write Cycle Wait Select
These bits specify the number of wait states to be inserted
into the initial normal write cycle and page write cycle.
00000: 0 wait states
:
11111: 31 wait states
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 280 of 1868
REJ09B0372-0100