SH7205 Datasheet, PDF (1427/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

VICLK
(27 MHz)
VIHSYNC
VICLKENB
VIVSYNC
Section 26 2D Graphics Engine (2DG)
Each signal input from the video decoder is synchronous with the rising edge of VICLK (for both NTSC/PAL).
Figure 26.7 Relations between Externally Input Sync Signal and VICLK
DCLKIN
HSYNC_dck
(Internal)
The WPH bits
in the
MGR_MIXHTMG
register
The ALLPH bits in the
MGR_MIXHS register
HVLD_dck
(Internal)
VSYNC_dck
(Internal)
The PDPH bits in the
MGR_MIXHTMG register
The VLDPH bits in the
MGR_MIXHS register
Each internally generated sync signal is synchronous with the rising edge of DCLKIN (for both NTSC/PAL).
Figure 26.8 Relations between Internal Generated Sync Signals and DCLKIN
Rev. 1.00 Mar. 25, 2008 Page 1395 of 1868
REJ09B0372-0100