SH7205 Datasheet, PDF (917/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
Figure 19.2 shows a block diagram of the SSIF module.
Serial audio bus
SSIDATA
SSISCK
SSIF module
Peripheral bus
Interrupt/DMA
request
Control
circuit
Registers:
SSICR
SSISR
SSIFCR
SSIFSR
SSIFDR (8-stage FIFO)
SSITDR
SSIRDR
MSB
Shift register
LSB
Serial clock control
Divider
SSIWS
Bit counter
EXTAL
XTAL
CKIO
AUDIO_CLK
AUDIO_X1
AUDIO_X2
[Legend]
SSICR:
SSISR:
SSITDR:
SSIRDR:
SSIFCR:
SSIFSR:
SSIFDR:
Control register
Status register
Transmit data register
Receive data register
FIFO control register
FIFO status register
FIFO data register
Figure 19.2 Block Diagram of SSIF
Rev. 1.00 Mar. 25, 2008 Page 885 of 1868
REJ09B0372-0100