SH7205 Datasheet, PDF (431/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.9 DMA Control Register B (DMCNTBn)
DMCNTBn controls whether to enable or disable DMA transfer, transfer enable clearing, and
internal status clearing. This register can also reference the DMA request status.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
DEN
-
-
-
-
-
-
- DREQ
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R
R
R
R
R
R
R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
- ECLR -
-
-
-
-
-
- DSCLR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R
R
R
R
R
R
R R/W
Initial
Bit
Bit Name Value
31 to 25 
All 0
24
DEN
0
23 to 17 
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should always
be 0.
R/W DMA Transfer Enable
This bit is used to enable or disable DMA transfer. Clearing this
bit to 0 disables DMA transfer on the channel. Setting this bit to
1 enables DMA transfer on the channel (for DMA transfer
activation, see section 11.4.3, DMA Activation). Even if this bit
is cleared to 0, the DMA request bit (DREQ) changes according
to the DMA request input to the DMAC. If the DMA transfer
enable clear bit (ECLR) is 1, this bit is automatically cleared to
0 when the DMA transfer end condition is detected. Clearing
this bit to 0 during DMA transfer also enables you to stop the
channel after the current single operand transfer is completed
(for details, see section 11.6, Suspending, Restarting, and
Stopping of DMA Transfer).
0: DMA transfer disabled
1: DMA transfer enabled
R Reserved
These bits are always read as 0. The write value should always
be 0.
Rev. 1.00 Mar. 25, 2008 Page 399 of 1868
REJ09B0372-0100