SH7205 Datasheet, PDF (75/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
1.6 Bus Structure
The bus structure of this LSI largely consists of CPU buses, internal buses, and peripheral buses.
The bus master of the CPU bus is a CPU. Each of the CPUs (CPU0 and CPU1) is provided with a
CPU bus for its own use, allowing both CPUs to run independently. A CPU bus actually consists
of two buses: an instruction-fetch bus and a memory-access bus (Harvard architecture).
The circuit has multiple (four) internal buses. The master modules of the internal bus are the two
CPUs and the DMAC. CPU0 and CPU1 are connected to the internal bus via the CPU bus and a
bus bridge. The read port and write port of the DMAC act as master modules for the
corresponding buses. That is, CPU0, CPU1, the DMA read port, and the DMA write port are
individually connected to the corresponding internal buses. This allows each of the master
modules to occupy its own internal bus without bus arbitration.
The slave modules of the internal buses are multiple peripheral buses (including the external bus
and high-speed on-chip RAM access bus). On each internal bus, arbitration for bus mastership is
performed between internal buses (master modules), after which access to the individual
peripheral bus proceeds. In this LSI, internal modules called bus interface units (BIUs) perform
this bus mastership arbitration. Since the BIUs perform arbitration per slave module, multiple
accesses can proceed in parallel as long as access by each master module is to a different BIU.
However, if more than one attempt at access to a given BIU is made at the same time, arbitration
between the master modules is performed. The master module that failed to gain bus mastership is
kept waiting until it succeeds, and thus the multiple accesses are executed one after another. The
order of priority in bus-mastership arbitration is as follows: DMA write port > DMA read port >
CPU. The priority order of CPU0 and CPU1 alternates in a round-robin manner.
The peripheral buses are used for the connections with the on-chip peripheral modules.
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REJ09B0372-0100