SH7205 Datasheet, PDF (961/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
20.2 Architecture
The RCAN-TL1 device offers a flexible and sophisticated way to organise and control CAN
frames, providing the compliance to CAN2.0B Active and ISO-11898-1. The module is formed
from 5 different functional entities. These are the Micro Processor Interface (MPI), Mailbox,
Mailbox Control, Timer, and CAN Interface. The figure below shows the block diagram of the
RCAN-TL1 Module. The bus interface timing is designed according to the peripheral bus I/F
required for each product.
CAN Interface
REC
CRxn
CTxn
Can Core
TEC
BCR
Transmit Buffer
Receive Buffer
Control
Signals
Status
Signals
clkp
preset_n
pms_can_n
p_read_n
p_write_n
psize_n
pwait_can_n
pa
pd
IrQs
scan_mode
16-bit
peripheral
bus
Micro Processor
Interface
MCR
IRR
GSR
IMR
TTCR0 CMAX_TEW
RFTROFF
TSR
CCR
TCNTR
CYCTR
RFMK
TCMR0
TCMR1
TCMR2
TTTSEL
16-bit Timer
TXPR
TXCR
RXPR
TXACK
ABACK
RFPR
MBIMR
UMSR
Mailbox Control
Mailbox0 Mailbox8 Mailbox16 Mailbox24
Mailbox1 Mailbox9 Mailbox17 Mailbox25
Mailbox2 Mailbox10 Mailbox18 Mailbox26
Mailbox3 Mailbox11 Mailbox19 Mailbox27
Mailbox4 Mailbox12 Mailbox20 Mailbox28
Mailbox5 Mailbox13 Mailbox21 Mailbox29
Mailbox6 Mailbox14 Mailbox22 Mailbox30
Mailbox7 Mailbox15 Mailbox23 Mailbox31
Mailbox 0 to 31 (RAM)
control0
LAFM
DATA
Mailbox0 Mailbox8 Mailbox16 Mailbox24
Mailbox1 Mailbox9 Mailbox17 Mailbox25
Mailbox2 Mailbox10 Mailbox18 Mailbox26
Mailbox3 Mailbox11 Mailbox19 Mailbox27
Mailbox4 Mailbox12 Mailbox20 Mailbox28
Mailbox5 Mailbox13 Mailbox21 Mailbox29
Mailbox6 Mailbox14 Mailbox22 Mailbox30
Mailbox7 Mailbox15 Mailbox23 Mailbox31
Mailbox 0 to 31 (register)
control1
Timestamp
Tx-Trigger Time
TT control
Figure 20.1 RCAN-TL1 architecture
Rev. 1.00 Mar. 25, 2008 Page 929 of 1868
REJ09B0372-0100