SH7205 Datasheet, PDF (498/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.4 CCLR0 to CCLR2 (Channels 0, 3, and 4)
Bit 7
Channel CCLR2
Bit 6
CCLR1
Bit 5
CCLR0
Description
0, 3, 4
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
1
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*¹
1
0
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/input
capture*²
1
0
TCNT cleared by TGRD compare match/input
capture*²
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*¹
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 12.5 CCLR0 to CCLR2 (Channels 1 and 2)
Bit 7
Bit 6
Channel Reserved*² CCLR1
Bit 5
CCLR0
Description
1, 2
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
1
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*¹
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.
Rev. 1.00 Mar. 25, 2008 Page 466 of 1868
REJ09B0372-0100