SH7205 Datasheet, PDF (151/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
• Mode 2
In mode 2, the CKIO pin functions as an input pin and draws an external clock signal. The
PLL circuit shapes waveforms and the frequency is multiplied according to the frequency
control register setting before the clock is supplied to the LSI. The frequency range of CKIO is
from 40 to 66.66 MHz. The internal clock frequency is quarter the CKIO pin frequency
multiplied by the frequency multiplication rate of the PLL circuit and the division ratio of the
divider 2. To reduce current, pull up the EXTAL pin and open the XTAL pin when the LSI is
used in mode 2. When USB is not used, pull up the USB_X1 pin and open the USB_X2 pin.
• Mode 3
In mode 3, a clock is input from the USB_X1 pin or the crystal oscillator. The external clock is
input through this pin and a waveform is shaped in the PLL circuit. Then the frequency is
multiplied according to the frequency control register setting before the clock is supplied to the
LSI. The frequency of CKIO is 48 MHz (USB_X1/crystal resonator). The internal clock
frequency is quarter the USB_X1 pin frequency multiplied by the frequency multiplication rate
of the PLL circuit and the division ratio of the divider 2. To reduce current, pull up the
EXTAL pin and open the XTAL pin when the LSI is used in mode 3. When the USB crystal
resonator is not used, open the USB_X2 pin.
Rev. 1.00 Mar. 25, 2008 Page 119 of 1868
REJ09B0372-0100