SH7205 Datasheet, PDF (375/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Single read
CKIO
SDRAM command
ACT DSL RD PRA DSL
Data bus
d
DRCD
(ACT-RD)
DCL
(RD-d)
DRAS
(ACT-PRA)
DPCG
(PRA-next)
ACT: Row and bank activation command
RD: Read command
DSL: Deselect command
PRA: Precharge-all-banks command
Note: If the interval set in DRAS ends before RD, PRA is issued in the cycle after RD.
Figure 10.36 Single Read Timing Example 2
Single read
CKIO
SDRAM command
ACT DSL RD PRA DSL
Data bus
d
DRCD
(ACT-RD)
DCL
(RD-d)
DRAS
(ACT-PRA)
DPCG
(PRA-next)
ACT: Row and bank activation command
RD: Read command
DSL: Deselect command
PRA: Precharge-all-banks command
Figure 10.37 Single Read Timing Example 3
Rev. 1.00 Mar. 25, 2008 Page 343 of 1868
REJ09B0372-0100