SH7205 Datasheet, PDF (810/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.3 shows a sample flowchart for initializing the SCIF.
Start of initialization
Clear the TE and RE bits in SCSCR to 0
Set the TFRST and RFRST bits in SCFCR to 1
After reading flags ER, DR, and BRK in SCFSR,
and each flag in SCLSR, write 0 to clear them
Set the CKE1 and CKE0 bits in SCSCR
(leaving bits TIE, RIE, TE, and RE cleared to 0)
[1]
Set data transfer format in SCSMR
[2]
Set the BGDM and ABCS bits in SCEMR
Set value in SCBRR
[3]
Set the RTRG1, RTRG0, TTRG1, TTRG0, and
MCE bits in SCFCR, and
clear TFRST and RFRST bits to 0
PFC setting for external pins used
SCK, TxD, RxD
[4]
Set the TE and RE bits in SCSCR to 1,
[5]
and set the TIE, RIE, and REIE bits
End of initialization
[1] Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
[2] Set the data transfer format in
SCSMR.
[3] Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
[4] Sets PFC for external pins used.
Set as RxD input at receiving and
TxD at transmission.
However, no setting for SCK pin is
required when CKE[1:0] is 00.
In the case when internal synchronous
clock output is set, the SCK pin starts
outputting the clock at this stage.
[5] Set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits. Setting the TE and RE bits
enables the TxD and RxD pins to be
used.
When transmitting, the SCIF will go
to the mark state; when receiving,
it will go to the idle state, waiting for
a start bit.
Figure 16.3 Sample Flowchart for SCIF Initialization
Rev. 1.00 Mar. 25, 2008 Page 778 of 1868
REJ09B0372-0100