SH7205 Datasheet, PDF (1354/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
(2) Transfer to and from memory via enhanced bus by interrupt
Start
Same as for process (a)
Write 1 to iERR and iNEND bits
in interrupt enable register
Write following values to bits 7 to 0
in ATAPI control register:
0m100101 for ATAPI device read
0m100001 for ATAPI device write
Note: Set m to the same value as the M/S bit.
Yes
Interrupt occurred?
No
Write 0 to iERR and iNEND bits
in interrupt enable register
Process (c)
Yes
ERR = 0 and NED = 1?
No
Clear ATAPI status register
Clear ATAPI status register
Error processing
End
Figure 25.7 Transfer to and from Memory via Enhanced Bus by Interrupt
Rev. 1.00 Mar. 25, 2008 Page 1322 of 1868
REJ09B0372-0100