SH7205 Datasheet, PDF (350/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Function/Operation Register Name Conditions
Mode register settings SD0MOD,
SD1MOD*²
• SDRAM access disabled (set in SDRAMCm*¹)
• Self-refresh disabled (DSFEN/DSFENCI = 0)
• Power-down disabled (DPWD/DPWDCI = 0)
• Deep-power-down disabled (DDPD/DDPDCI = 0)
Clock stop control signal SDCKSCNT
settings
• Deep-power-down disabled (DDPD/DDPDCI = 0)
Notes: 1. After writing 0 to EXENB, make sure that the EXENB bit has been cleared to 0.
2. Before rewriting this bit, make sure that all status bits in the SDRAM status register
(SDSTR) have been cleared to 0.
(4) Self-Refresh
Transition to and from self-refresh mode is controlled by means of settings to SDRAM refresh
control register 0 (SDRFCNT0). Transition to and from self-refresh mode takes place
simultaneously for all channels. After settings for self-refresh mode have been made, this LSI
continues in the self-refresh state even when it is placed on software standby or deep standby. The
self-refreshing state is also maintained after interrupt-initiated recovery from standby state.
However, the setting for the HIZBCS bit in the HIZCR register must be 0, and the CKE and other
pins must be driven even in standby mode. With regard to the HIZCE register, refer to section 30,
Power-Down Modes.
An auto-refresh cycle operation takes place immediately before transition to self-refresh mode.
While in self-refresh mode the CKE signal is low level. Immediately after recovery from self-
refresh mode, an auto-refresh cycle is triggered.
Figure 10.8 shows the timing of transition to self-refresh mode, and figure 10.9 shows the timing
of recovery from self-refresh mode.
Rev. 1.00 Mar. 25, 2008 Page 318 of 1868
REJ09B0372-0100