SH7205 Datasheet, PDF (17/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

12.3.18 Timer Output Control Register 1 (TOCR1) .......................................................... 512
12.3.19 Timer Output Control Register 2 (TOCR2) .......................................................... 515
12.3.20 Timer Output Level Buffer Register (TOLBR) .................................................... 518
12.3.21 Timer Gate Control Register (TGCR) .................................................................. 519
12.3.22 Timer Subcounter (TCNTS) ................................................................................. 521
12.3.23 Timer Dead Time Data Register (TDDR)............................................................. 522
12.3.24 Timer Cycle Data Register (TCDR) ..................................................................... 522
12.3.25 Timer Cycle Buffer Register (TCBR)................................................................... 523
12.3.26 Timer Interrupt Skipping Set Register (TITCR) ................................................... 523
12.3.27 Timer Interrupt Skipping Counter (TITCNT)....................................................... 525
12.3.28 Timer Buffer Transfer Set Register (TBTER) ...................................................... 526
12.3.29 Timer Dead Time Enable Register (TDER).......................................................... 528
12.3.30 Timer Waveform Control Register (TWCR) ........................................................ 529
12.3.31 Bus Master Interface............................................................................................. 530
12.4 Operation ........................................................................................................................... 531
12.4.1 Basic Functions..................................................................................................... 531
12.4.2 Synchronous Operation......................................................................................... 537
12.4.3 Buffer Operation ................................................................................................... 539
12.4.4 Cascaded Operation .............................................................................................. 543
12.4.5 PWM Modes ......................................................................................................... 548
12.4.6 Phase Counting Mode........................................................................................... 553
12.4.7 Reset-Synchronized PWM Mode.......................................................................... 560
12.4.8 Complementary PWM Mode................................................................................ 563
12.4.9 A/D Converter Start Request Delaying Function.................................................. 603
12.4.10 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 607
12.5 Interrupt Sources................................................................................................................ 608
12.5.1 Interrupt Sources and Priorities ............................................................................ 608
12.5.2 DMAC Activation................................................................................................. 610
12.5.3 A/D Converter Activation..................................................................................... 610
12.6 Operation Timing............................................................................................................... 612
12.6.1 Input/Output Timing ............................................................................................. 612
12.6.2 Interrupt Signal Timing......................................................................................... 619
12.7 Usage Notes ....................................................................................................................... 623
12.7.1 Module Standby Mode Setting ............................................................................. 623
12.7.2 Input Clock Restrictions ....................................................................................... 623
12.7.3 Caution on Period Setting ..................................................................................... 624
12.7.4 Contention between TCNT Write and Clear Operations...................................... 624
12.7.5 Contention between TCNT Write and Increment Operations............................... 625
12.7.6 Contention between TGR Write and Compare Match .......................................... 626
12.7.7 Contention between Buffer Register Write and Compare Match ......................... 627
Rev. 1.00 Mar. 25, 2008 Page xvii of xxxii