SH7205 Datasheet, PDF (156/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
Bit
14
13, 12
11, 10
Initial
Bit Name Value R/W
CKOEN2 0
R/W
CKOEN 00
R/W
[1:0]

All 0 R
Description
Clock Output Enable 2
Specifies whether the CKIO pin outputs clock signals or is
fixed at low during a change of the frequency multiplication
rate of the PLL circuit.
If this bit is set to 1, the CKIO pin is fixed at low during a
change of the frequency multiplication rate of the PLL
circuit. Therefore, the malfunction of an external circuit
caused by an unstable CKIO clock during a change of the
frequency multiplication rate of the PLL circuit can be
prevented. In clock operating mode 2, the CKIO pin
functions as an input regardless of the value of these bits.
0: An unstable clock is output.
1: A low level is output.
Clock Output Enable
Specifies whether the CKIO pin outputs a clock signal, or is
tied to a fixed level or high impedance (Hi-Z) during normal
operation, standby mode, and exit from standby mode.
If these bits are set to 01, the CKIO pin is fixed at low
during standby mode or cancellation of standby mode.
Therefore, the malfunction of an external circuit caused by
an unstable CKIO clock during exit from standby mode can
be prevented. In clock operating mode 2, the CKIO pin
functions as an input regardless of the value of these bits.
In standby mode, the state in normal mode is retained.
Normal operation
Standby mode
00 Output
Output off (Hi-Z)
01 Output
Low-level output
10 Output
Output (unstable clock output)
11 Output off (Hi-Z)
Output off (Hi-Z)
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 124 of 1868
REJ09B0372-0100