SH7205 Datasheet, PDF (1185/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.8 DMA-FIFO Bus Configuration Registers (D0FBCFG, D1FBCFG)
D0FBCFG and D1FBCFG perform access control of the D0FIFO and D1FIFO ports.
These registers are initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
— DFACC[1:0] —
—
—
—
—
—
— TENDE —
—
—
—
Initial value: -
-
0
0
-
-
-
-
-
-
-
0
-
-
-
-
R/W: R
R R/W R/W R
R
R
R
R
R
R R/W R
R
R
R
Bit
Bit Name
15, 14 
Initial
Value
R/W
Undefined R
13, 12 DFACC[1:0] 00
R/W
11 to 5 
Undefined R
4
TENDE
0
R/W
3 to 0 
Undefined R
Description
Reserved
Undefined values are read from these bits. The write
value should always be 0.
These bits specify an access mode of the
corresponding FIFO port.
Select the transfer data per one operand. For detail,
see section 24.4.4 (4), DMA transfer (D0FIFO,
D1FIFO Ports).
00: Single-data access mode (initial value)
01: 16-byte continuous access mode
10: 32-byte continuous access mode
11: Setting prohibited
Reserved
Undefined values are read from these bits. The write
value should always be 0.
DMA Transfer End Sampling Enable
Controls acceptance of DMA transfer end signal from
the direct memory access controller (DMAC), which
is output at the end of DMA transfer. For detail, see
section 24.4.4 (4), DMA transfer (D0FIFO, D1FIFO
Ports).
0: DMA transfer end signal is not sampled
1: DMA transfer end signal is sampled
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1153 of 1868
REJ09B0372-0100