SH7205 Datasheet, PDF (1889/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Index
Numerics
16-bit/32-bit displacement ........................ 55
2D Graphics Engine (2DG) .................. 1327
2DG timing ........................................... 1837
A
A/D conversion time
(multi mode and scan mode)................. 1052
A/D conversion time (single mode)...... 1051
A/D conversion timing ......................... 1051
A/D converter (ADC) ........................... 1033
A/D converter activation......................... 610
A/D converter characteristics................ 1844
A/D converter start request delaying
function................................................... 603
A/D trigger input timing ....................... 1798
Absolute address....................................... 55
Absolute address accessing....................... 55
Absolute maximum ratings................... 1751
AC characteristics................................. 1763
AC characteristics measurement
conditions ............................................. 1843
Accessing CS space ................................ 302
Accessing SDRAM................................. 316
Address array.................................. 244, 258
Address errors......................................... 145
Address map ........................................... 267
Addressing modes..................................... 56
Analog input pin ratings ....................... 1057
AND/NAND flash memory controller
(FLCTL) ............................................... 1067
Arithmetic operation instructions ............. 75
AT attachment packet interface
(ATAPI)................................................ 1299
ATAPI timing ....................................... 1810
B
Bit manipulation instructions .................... 86
Bit synchronous circuit ........................... 879
Boundary scan....................................... 1598
Branch instructions ................................... 80
Break detection and processing............... 796
Break on data access cycle...................... 236
Break on instruction fetch cycle.............. 235
Bulk transfers........................................ 1290
Bus state controller (BSC) ...................... 263
Bus timing............................................. 1770
C
Cache ...................................................... 243
Cache structure........................................ 243
Calculating exception handling vector
table addresses ........................................ 140
CAN bus interface................................. 1028
CAN interface ......................................... 931
Canceling software standby mode
(WDT)..................................................... 693
Cascaded operation ................................. 543
Caution on period setting ........................ 624
Changing the division ratio ..................... 130
Changing the multiplication rate............. 128
Changing the PLL multiplication ratio ... 693
Clock frequency control circuit............... 115
Clock operating modes ........................... 118
Clock pulse generator (CPG) .................. 113
Clock timing ......................................... 1764
Clocked synchronous serial format......... 869
CMCNT count timing ............................. 677
Coherency of cache and external
memory ................................................... 258
Command access mode......................... 1105
Compare match timer (CMT) ................. 671
Rev. 1.00 Mar. 25, 2008 Page 1857 of 1868
REJ09B0372-0100