SH7205 Datasheet, PDF (333/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Bit
7 to 0
Initial
Bit Name Value
DCKSC H'0F
[7:0]
Section 10 Bus State Controller (BSC)
R/W Description
R/W Clock Stop Cycle Count Setting
These bits specify the interval from the point at which the
deep-power-down transition command is issued until the
clock stop control function stops CKIO (low level), and the
interval from the point at which CKIO starts operating until
the recover command is issued.
00000000: 0 cycles
:
00001111: 15 cycles
:
11111111: 255 cycles
10.4.18 AC Characteristics Switching Register (ACSWR)
In clock mode 0 or 1, make the AC characteristics switching register (ACSWR) setting if SDRAM
is to be used. In clock mode 2 or 3, do not change the initial ACSWR setting.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
ACOSW[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W
Bit
31 to 4
Initial
Bit Name Value

All 0
3 to 0 ACOSW 0000
[3:0]
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W AC Characteristics Switching
These bits specify AC characteristics switching.
0000: Does not extend the delay time.
TBD: Switches AC characteristics and extends the delay
time.
Other than above: Setting prohibited
Rev. 1.00 Mar. 25, 2008 Page 301 of 1868
REJ09B0372-0100