SH7205 Datasheet, PDF (1214/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Bit
10
9
8
7
6 to 4
Initial
Bit Name Value
R/W
BEMP
0
R
NRDY
0
R
BRDY
0
R
VBSTS
Undefined R
DVSQ[2:0] *¹
R
Description
Buffer Empty Interrupt Status
This bit is set to 1 when at least one PIPEBEMP bit
in BEMPSTS is set to 1 among the PIPEBEMP bits
corresponding to the PIPEBEMPE bits in BEMPENB
to which 1 has been set. This bit is cleared when all
the bits in BEMPSTS have been cleared.
0: BEMP interrupt has not occurred
1: BEMP interrupt has occurred
Buffer Not Ready Interrupt Status
This bit is set to 1 when at least one PIPENRDY bit
in NRDYSTS is set to 1 among the PIPENRDY bits
corresponding to the PIPENRDYE bits in NRDYENB
to which 1 has been set. This bit is cleared when all
the bits in NRDYSTS have been cleared.
0: NRDY interrupt has not occurred
1: NRDY interrupt has occurred
Buffer Ready Interrupt Status
This bit is set to 1 when at least one PIPEBRDY bit
in BRDYSTS is set to 1 among the PIPEBRDY bits
corresponding to the PIPEBRDYE bits in BRDYENB
to which 1 has been set. This bit is cleared when all
the bits in BRDYSTS have been cleared.
0: BRDY interrupt has not occurred
1: BRDY interrupt has occurred
VBUS Input Status
This bit reflects the level of the signal input to the
VBUS pin. The VBUS input status in this bit needs a
control program to prevent chattering.
0: The VBUS pin is low level.
1: The VBUS pin is high level.
Device State*⁶
000: Powered state
001: Default state
010: Address state
011: Configured state
1xx: Suspended state
Rev. 1.00 Mar. 25, 2008 Page 1182 of 1868
REJ09B0372-0100