SH7205 Datasheet, PDF (1335/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
Table 25.4 ATAPI Interface Control Register Map
(These resisters are allocated to this module.)
Address
Register Name
Abbreviation
Access
Type Access Size*
H'FFFECC80 ATAPI control
ATAPI_CONTROL
R/W 32
H'FFFECC84 ATAPI status
ATAPI_STATUS
R/W 32
H'FFFECC88 Interrupt enable
ATAPI_INT_ENABLE
R/W 32
H'FFFECC8C PIO timing
ATAPI_PIO_TIMING
R/W 32
H'FFFECC90 Multiword DMA timing ATAPI_MULTI_TIMING
R/W 32
H'FFFECC94 Ultra DMA timing
ATAPI_ULTRA_TIMING R/W 32
H'FFFECC9C DMA start address
ATAPI_DMA_START_ADR R/W 32
H'FFFECCA0 DMA transfer count ATAPI_DMA_TRANS_CNT R/W 32
H'FFFECCA4 ATAPI control 2
ATAPI_CONTROL2
R/W 32
H'FFFECCB0 ATAPI signal status ATAPI_SIG_ST
R
32
H'FFFECCBC Byte swap
ATAPI_BYTE_SWAP
R/W 32
Note: * These registers must be accessed in longword (32-bit) units. Byte and word accesses
are prohibited.
Rev. 1.00 Mar. 25, 2008 Page 1303 of 1868
REJ09B0372-0100