SH7205 Datasheet, PDF (175/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
(3) Power-On Reset Initiated by WDT
Each CPU has a watchdog timer (WDT).
When either or both of the WDTs are set so that a power-on reset occurs in watchdog timer mode,
and the WTCNT (or WTCNTs) of the WDT (or WDTs) overflows, this LSI enters the power-on
reset state.
In this case, WRCSR of the WDT and FRQCR of the CPG are not initialized by the reset signal
generated by the WDT.
If a reset caused by the RES pin or the H-UDI reset assert command occurs simultaneously with a
reset caused by WDT overflow, the reset caused by the RES pin or the H-UDI reset assert
command has priority, and the WOVF bit in WRCSR is cleared to 0. When power-on reset
exception handling is started by the WDT, the CPU operates in the same way as when a power-on
reset was caused by the RES pin.
Rev. 1.00 Mar. 25, 2008 Page 143 of 1868
REJ09B0372-0100