SH7205 Datasheet, PDF (316/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
6 to 4 CSWOFF 000
[2:0]
R/W Write Operation CS Delay Cycle Select
These bits specify the number of cycles from the end of
the wait cycle (negation of the WE3 to WE0 signals) to the
negation of the CS5 to CS0 signals during write access
operation.
000: 0 wait states
:
111: 7 wait states
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0 CSROFF 111
[2:0]
R/W Read Operation CS Delay Cycle Select
These bits specify the number of cycles from the end of
the wait cycle (negation of the RD signal) to the negation
of the CS5 to CS0 signals during read access operation.
000: 0 wait states
:
111: 7 wait states
Notes: 1. Select each number of wait states or delay cycles according to the configuration of your
system.
2. Writing to the CSn wait control register 2 (CS2WCNTn) must be done while the CSC for
the corresponding channel is disabled (EXENB = 0). Only channel 0 (CS0) is allowed
for writing to the register without disabling the CSC (EXENB = 1). To write to
CS2WCNT0 with CSC enabled, satisfy all of the following conditions:
• Stop the DMAC.
• Keep the CPU other than the one that is going to rewrite the register from accessing
CS0 (including access for instruction fetch). For example, if CPU0 is going to rewrite
the register, make CPU1 stay looping by a program copied to on-chip memory, or put
CPU1 in a sleep state.
• Do not perform data write access to CS0 after a reset is released but before the
register is rewritten.
3. Each bit must be set under the following restrictions.
When page access is disabled (PRENB, PWENB = 0)
CSON ≤ min (CSRWAIT, CSWWAIT), WDON ≤ CSWWAIT,
WRON ≤ CSWWAIT, RDON ≤ CSRWAIT
WDOFF ≤ CSWOFF
When page access is enabled (PRENB = 1 or PWENB = 1)
Rev. 1.00 Mar. 25, 2008 Page 284 of 1868
REJ09B0372-0100