SH7205 Datasheet, PDF (329/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.4.15 SDRAMm Mode Register (SDmMOD) (m = 0, 1)
SDmMOD specifies the values to be written to the SDRAM mode register or extended mode
register. Writing to this register causes a mode register set command or extended mode register set
command to be issued automatically to SDRAM.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15
-
Initial value: 0
R/W: R
14
-
R/W
13
-
R/W
12
-
R/W
11
-
R/W
10
-
R/W
9
-
R/W
8
7
DMR[14:0]
-
-
R/W R/W
6
-
R/W
5
-
R/W
4
-
R/W
3
-
R/W
2
-
R/W
1
-
R/W
0
-
R/W
Initial
Bit
Bit Name Value R/W
31 to 15 
All 0
R
14 to 0 DMR
[14:0]
Undefined R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Mode Register Setting
Writing to these bits causes a mode register set command
or extended mode register set command to be issued to
SDRAM. The setting of the DMR bits is output as the A16
to A2 signal. SDRAM distinguishes between the mode
register set command and the extended mode register set
command based on their bank address.
Write operation: A mode register set command is issued.
DMR bit
b14 B13 …
b0
↓↓
↓
A16 to A2 signal A16 A15 …
A2
Notes: The following points should be kept in mind regarding SDRAMm mode register settings.
1. Make sure to set a burst length of 1 for SDRAM. Operation cannot be guaranteed with
settings other than a burst length of 1.
2. The SDRAM column latency must match the setting of the SDRAM controller column
latency setting bits (DCL) in SDRAMC. Operation cannot be guaranteed if the latency
settings do not agree.
3. Make sure the status bits (DSRFST, DPWDST, DDPDST, and DMRSST) in the
SDRAM status register (SDSTR) are all cleared to 0.
Rev. 1.00 Mar. 25, 2008 Page 297 of 1868
REJ09B0372-0100