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SH7205 Datasheet, PDF (1054/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Section 20 Controller Area Network (RCAN-TL1)
20.4.4 Message Receive Sequence
The diagram below shows the message receive sequence.
CAN Bus
RCAN-TL1
End Of Arbitration Field
IDLE
End Of Frame
Valid CAN-ID Received
Loop (N = 31; N ≥ 0; N = N - 1)
N=N-1
Valid CAN Frame Received
Compare ID with
Mailbox[N] + LAFM[N]
(if MBC is config to receive)
Yes
No
ID Matched?
No
Yes
N = 0?
Yes
Store Mailbox-Number[N]
and go back to idle state
OverWrite
RXPR[N]
(RFPR[N])
Already Set?
No
Yes
MSG
OverWrite or
OverRun?
(NMC)
•Store Message by Overwriting
•Set UMSR
•Set IRR9 (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR9 = 0)
•Set RXPR[N] (RFPR[N])
•Set IRR1 (IRR2) (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR1 (IMR2) = 0)
Interrupt signal
OverRun
•Reject Message
•Set UMSR
•Set IRR9 (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR9 = 0)
•Set RXPR[N] (RFPR[N]) *
Interrupt signal
•Store Message
•Set RXPR[N] (RFPR[N])
•Set IRR1 (IRR2) (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR1 (IMR2) = 0)
Interrupt signal
Exit Interrupt Service
Routine
Check and clear
UMSR[N] **
Check and clear
UMSR[N] **
Write 1 to RXPR[N] Write 1 to RFPR[N]
Read Mailbox[N]
Read Mailbox[N]
Read RXPR[N] = 1
Read RFPR[N] = 1
Yes
IRR[1]
No
set?
Read IRR
CPU received interrupt due to CAN Message Reception
Notes: 1. Only if CPU clears RXPR[N]/RFPR[N] at the same time that UMSR is set in overrun, RXPR[N]/RFPR[N] may be set again even though the
message has not been updated. TimeStamp may also be updated, however it can be read properly before clearing RXPR[N]/RFPR[N].
2. In case overwrite configuration (NMC = 1) is used for the Mailbox N the message must be discarded when UMSR[N] = 1, UMSR[N] cleared
and the full Interrupt Service Routine started again. In case of overrun configuration (NMC = 0) is used clear again RXPR[N]/RFPR[N]/
UMSR[N] when UMSR[N] = 1 and consider the message obsolate.
Figure 20.24 Message receive sequence
Rev. 1.00 Mar. 25, 2008 Page 1022 of 1868
REJ09B0372-0100